In the manufacture of integrated circuits, interconnect structures are generally formed on a semiconductor substrate using a dual damascene process. Such a process begins with a trench being etched into a dielectric layer and filled with a barrier layer, an adhesion layer, and a seed layer. A physical vapor deposition (PVD) process, such as a sputtering process, or an atomic layer deposition (ALD) process, may be used to deposit the barrier layer into the trench. The barrier layer prevents copper, for example, from diffusing into the underlying dielectric layer. As device dimensions scale down, the aspect ratio of the trench may become more aggressive as the trench becomes narrower. This gives rise to issues such as trench overhang during a barrier layer formation, for example, which may lead to pinched-off trench openings and inadequate gapfill.